Imec recently presented a highly robust spin-orbit torque magnetic random-access memory (SOT-MRAM) for high-performance computing. Compared to traditional RAM technologies, MRAM can store more data using less energy, making Imec’s innovation a promising step toward higher memory performance.
At a considerably lower size, Imec’s SOT-MRAM technology has brought MRAM one step closer to being a practical replacement for traditional SRAM. Image used courtesy of Imec
MRAM in itself is not a new invention, with early products ranging back to 2006. It is, however, considerably newer than SRAM or DRAM. MRAM currently faces many issues because of the complexity of magnetic spin devices, particularly with dense integration in traditional CMOS processes. Now, new techniques such as SOT-MRAM may lead the charge to improve MRAM performance.
This article explores how SOT-MRAM compares to other MRAM architectures. In addition, we will discuss how Imec researchers optimized a SOT-MRAM design to create a scalable, robust memory technology.
Spintronics as Memory
At its core, SOT-MRAM stores information in the form of electron spin. Using magnetic fields, the spin of quantum particles can be modified to encode 1s and 0s for later use in a nonvolatile fashion, saving on power for densely integrated memory chips.
Magnetic tunnel junctions use the spin of one layer’s electrons to modulate the resistance of the junction, encoding the information using magnetics. Image used courtesy of Antaios
Although the underlying physics are quite complicated, modern MRAM technology fundamentally relies on the performance of magnetic tunnel junctions (MTJs) that consist of two ferromagnetic layers, each with its own unique spin. When the spin directions align, the resistance of the MTJ is lower, allowing the state to be easily read using CMOS technology.
Scaling SOT Memory
Imec’s MRAM differs from other types of memory because of the method by which magnetic information is changed. Compared to spin-transfer torque (STT) MRAM, another type of MRAM, SOT-MRAM offers virtually unlimited read/write endurance since no current is passed through the MTJ. Instead, an adjacent in-plane current is used to improve the robustness and prevent thermal-related issues.
Imec’s latest SOT development reduces the size of a SOT track considerably, providing more efficient performance with more integration potential. Image used courtesy of Imec
In addition, Imec’s latest SOT-MRAM technology is more scalable than conventional MRAM, opening doors to practical deployment. Since the size of the SOT track is scaled along with the MTJ, power waste is reduced while the occupied space is shrunk, allowing for denser integration and tighter bit packing. According to the researchers, this scaling resulted in a switching energy of ~100 fJ per bit—a 63% reduction compared to traditional designs.
A Benefit to HPC and Edge Applications Alike
While MRAM may never replace DRAM and SRAM, it provides a new option for efficient, nonvolatile memory that may benefit not only HPC applications but also any field that deals with heavy memory transfer, such as AI/ML training. These MRAM improvements can also benefit edge devices, where every bit of performance counts.
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